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Free Intellectual PropertiesSDRAM Controllerdesign type : Verilog
Description *This synthesizable IP lets you use a large capacity SDRAM in your designs as though it were a SRAM. *The several SDRAM configuration are available, including 1M x 16 and 2M x 32. With minor modifications, it is possible to target other capacities. *The IP handles all of the low level tasks such a power-up SDRAM initialization, refresh generation and arbitration. *Built-in syntehsizable test cores allows you to perform I/Os to the SDRAM to verify its performance and features *The host interface is "SRAM" like. That is, one byte/half-word/word at a time. Presently does not support burst transfers. *The IP was tested on Altera 10K20 FPGA and Lattice 3256 CPLD/ 8840CPLD..successfully
A Word of Note There are a number of websites where you can get SDRAM controllers for free. Much of these cores have, however, a verys specific host interface in mind, requiring that you modify your interface if you had already designed it. In addition, the cores are rather platform specific. That is, they employ built-in features of the specific FPGA/CPLD it is targeting. Most of the time, these features are not found on other FPGA/CPLDs. On the bright side, all of these reasons makes the SDRAM controller run very fast. The SDRAM controller core presented here is not platform specific. It has been tested on three major platforms: Xilinx,. Altera and Lattice, and has been sucessfully compiled, synthesized and simulated. The core is great if you have a bunch of SDRAMs lying around and would like to include on your next project, without so much being keen in hitting the specification limits. The core will support SDRAMs at up to 100MHz, however. Getting the core working at that speed on your platform is left for you to work on. The interface to the host is very much like that of a typical SRAM with a handshake. The host makes a read or write access, and if the SDRAM controller is busy, it will generate a "busy" output, which the host upon sampling must hold the bus. When the SDRAM controller deasserts the "busy", the host is ready to terminate the bus cycle. The first release of the core does not support burst mode transfers. Since this implies that the host and the SDRAM core needs to have a transfer protocol, I've tried to avoid getting into the myriad of processors with their own unique needs.
Documentation Initial documentation 72K PDF. A number of people have reported problems with unavailable font. I belive it is now fixed. Thanks to all those who reported the problem.
Pictures Prototype (16 bit wide version only) working on Altera UP1 board. Source Code There are several design files
Other Design Files If you're working on Xilinx, Altera or Lattice platforms with Foundation Base Express 2.1i, Max+PlusII 9.21 and ispExpert 7.0 packages, and would like to receive the complete "project directory" (which includes, simulation files, etc) please make a request to jlee@cmosexod.com, specifying you platform. They are not presented here due to the size of the files. Altera design files for 16 bit sdram version available. Download here.
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