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Free Intellectual Properties
Reliance - 1
EDA platform : ViewLogic
design type : Schematic
Description
- Reliance 1 is a general purpose fixed-point Digital Signal Processor (DSP) targeted for
implementing a real-time stereo equalizer in the form of cascaded digital band-pass
filters.
- 2 stage pipeline architecture (load opcode+operands / multiply ).
- The architecture is optimized to perform second order IIR systems in
transposed-canonical realization II, which is the most optimum (takes only 2 memory
locations) and the most stable for doing integer maths. Therefore by cascading N sets of
these you can implement just about any type of filters.
- The internal data path is 24 bits, but only 12x12 multiply (signed) is supported
- In order to allow fast execution and small code rom (flash or eeprom), upon power-up or
system reset, the code and filter coefficients, are loaded from the 8bit code-memory
(flash or eeprom) by the onboard boot-loader in to a faster 24bit wide SRAM, where
execution takes place.
- The IP contains controllers for Burr-Brown ADS7804 11 bit ADC and Analog Devices
ADS7804DACs.
- The prototype I've built was able to run at 0.625MIPS this does not mean you can't do
better. Obviously this rate did not allow me to run a 5 band stereo equalizer at 44Khz,
which I intended Realiance-1 to do.
Documentation
The following document contains a much more detailed documentation. It's a big file
with lots of pretty images and such. Word 95 format
reliance1_documentation.pdf
Design Files
Please contact me to obtain the schematic files.
Pictures of Prototype
This is a large page, so may take a while. Click here to see it
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