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FreeCore Function #11:
VGA Sync Generator
Module name: vga_sync
Current release: version 1.0, October 6, 1997
Contributed by: Rune Baeverrud
Introduction
Shown below is the schematic representation of the vga_sync
VGA Sync Generator:
This module makes it very easy to generate the signals required for output to an
industry standard VGA computer screen. A number of status output signals are provided for
easy synchronizing to external pixel data.
If you would like to do a simple functional test of the above module, you could try the
following diagram:
Module Parameters
| INPUT PORTS |
| SysClk |
System clock input. Normally, you would use a 25.175MHz clock input, as
this will output pixel data at the rate specified by the VGA standard. In this case - tie
the Enable input to VCC. |
| Enable |
One Enable high period corresponds to one output video pixel.You could double or
triple the input SysClk frequency - if doubling the input frequency, then you should
provide an Enable signal of 1/2 duty cycle. If tripling the input frequency, you should
provide 1/3 duty cycle on the Enable input. |
| OUTPUT PORTS |
| H_Sync |
Horizontal sync signal |
| V_Sync |
Vertical sync signal |
| Video |
Stays at '1' while H_Cnt is within the range [0,639] and V_Cnt is within the range
[0,479]. |
| Pix_En |
Goes to '1' for one SysClk period, once for every pixel, while H_Cnt is within the
range [0,639] and V_Cnt is within the range [0,479]. |
| Frame |
Goes to '1' for one SysClk period before each video frame. |
| H_Cnt[9..0] |
Horizontal position of the next pixel to be displayed on the VGA screen. Output is in
the range [0,799] but you should only output data when the value is within the range
[0,639]. |
| V_Cnt[9..0] |
Vertical position of the next pixel to be displayed on the VGA screen. Output is in
the range [0,524] but you should only output data when the value is within the range
[0,479]. |
NOTE: When you compile a design including the vga_sync
module, the timing analyzer may report a maximum clock frequency of about 50MHz. You could
probably still use a triple rate input clock at 75MHz if you like. Nothing is happening
inside the vga_sync while the Enable input is low, so
all signals will have plenty of time to stabilize before the next clock pulse arrive.
Enjoy!
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