Welcome to PLD World! 欢迎来到可编程逻辑器件的世界! http://pld.126.com

　

FreeCore Function #6:
I2C Controller Reference Design
Module name: I2C_test
Current release: version 3.0, January 30, 1998
Contributed by: Rune Baeverrud

Changes since version 2.0

  • Updated to reflect changes in div_by_n module.

Changes since version 1.0

  • Updated to reflect changes in I2C Controller core design - the asynchronous reset input has been added.

Description

Shown below is a sample schematic using the I2C controller.

f6_1.gif (7811 bytes)

The above schematic is suitable for interfacing to a 16 bit microprocessor. A few notes on the circuit:

  • system clock is 60MHz, div_by_n_DIVISOR=10 => 10MHz clock enable
  • I2C_clk_en = 10MHz => I2C_DIVISOR = 10MHz / 400kHz = 25.
  • b[] must be valid when WE (Write Enable) goes high
  • /IRQ is suitable for a processor with falling edge sensitive interrupt
  • polling operation is possible
  • remember to add external pull-ups on the SDA and SCL lines!

If you need 8-bit (or lower) operation, it should be an easy task to modify the circuit. You need to add some registers on the input, and some multiplexers at the output, with some address decoding logic. I will leave that part to you now!

                                                                                                返回

　

 编辑设计: 胡晟  技术顾问: 朱仁昌 Copyright 1999-2000 PLD World    http://pld.126.com