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FreeCore Function #1:
Divide By N Frequency Divider
Module name: div_by_n
Current release: version 2.0, January 30, 1998
Contributed by: Rune Baeverrud
Changes since version 1.0
- After a reset, Every_N will not go high until the end of the cycle.
- Previous input Enable has been renamed to cnt_en (count enable).
- An additional input sclr will clear the internal counter on the next SysClk positive
edge, regardless of the state of cnt_en.
- An additional output Q[] provides the current count value.
Description
The single most useful function I ever wrote just got better. I find myself using the
div_by_n module almost everywhere - as it is extremely useful for generating clock enable
signals. Shown below is a simple schematic using the div_by_n
module, and it also demonstrates the cascadability of the module:
...and this is how the simulator output of the above schematic looks like:
Ports & Parameters Description
| PARAMETERS |
| DIVISOR |
Divisor value. |
| INPUT PORTS |
| SysClk |
System clock input. |
| cnt_en |
The internal counter counts on the positive edge of SysClk whenever cnt_en is high.
Default value is VCC. |
| sclr |
The internal counter is cleared on the positive edge of SysClk whenever sclr is high,
regardless of the state of cnt_en. If both cnt_en and sclr is asserted, sclr will take
precedence. Default value is GND. |
| OUTPUT PORTS |
| Every_n |
(SysClk AND Enable) divided by DIVISOR, delayed by 1 SysClk cycle. |
| Q[] |
Current internal counter value. For instance - with a DIVISOR value of 7,
the counter will cycle through values 0..6 whic can be read at the Q[] output. |
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